Authors: Yun-Da Tsai, Mingjie Liu, Haoxing Ren

Published on: November 28, 2023

Impact Score: 8.22

Arxiv code: Arxiv:2311.16543

Summary

• What is new: Introduction of RTLFixer, a framework that combines Retrieval-Augmented Generation (RAG) and ReAct prompting for fixing syntax errors in Verilog code generated by LLMs.
• Why this is important: Approximately 55% of errors in LLM-generated Verilog are syntax-related, leading to compilation failures.
• What the research proposes: RTLFixer employs a novel debugging framework using RAG and ReAct prompting to enable LLMs to interactively debug and correct syntax errors in Verilog code.
• Results: RTLFixer corrected about 98.5% of syntax errors in the dataset, significantly increasing pass rates by 32.3% and 10.1% in VerilogEval-Machine and VerilogEval-Human benchmarks, respectively.

Technical Details

Technological frameworks used: RTLFixer, using Retrieval-Augmented Generation (RAG) and ReAct prompting

Models used: Large Language Models (LLMs)

Data used: VerilogEval benchmark, including 212 erroneous Verilog implementations

Potential Impact

Companies in the semiconductor and electronic design automation (EDA) industries could significantly benefit, potentially disrupting traditional syntax error debugging methods.

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